1. Field of the Invention
The present invention relates to the layout of conducting wires of a semiconductor memory, and is used, for example, for a semiconductor memory requiring a higher storage capacity.
2. Description of the Related Art
Recently, nonvolatile semiconductor memories such as NAND-type flash memories have been used as storage units in various electronic devices.
Higher storage capacities of the NAND-type flash memories are desired along with increasing functions of the electronic devices.
The NAND-type flash memory comprises a memory cell array section in which memory cells are formed, and a peripheral circuit section disposed on the periphery of the memory cell array section, and chip layout is extremely important for a higher memory capacity.
For example, while the miniaturization of the memory cells is prominently developing, misalignment during photolithography has to be taken into account to determine the sizes and pitches of conducting wires and contact holes in order to prevent the breaking and short circuit of the conducting wires and to improve reliability (e.g., refer to Jpn. Pat. Appln. KOKAI Publication No. 2002-151601).
For example, even if word lines are formed with minimum processing dimensions within a memory cell array by a line-and-space pattern, for example, lead wires made of a metal are required to connect the word lines to a word line driver.
Therefore, there is a necessity for a region to connect the word lines to the lead wires, and a word line lead area has to be secured on the periphery of the memory cell array.
Thus, considering a wiring line layout in the lead wire area is important to reduce the chip size of the NAND-type flash memory and improve its reliability.
Moreover, such a problem is not limited to the NAND-type flash memories, and a similar problem arises in a semiconductor integrated circuit such as a DRAM having a line-and-space wiring line structure.
The present invention proposes a technique for preventing the short circuit of conducting wires having a line-and-space pattern and reducing a chip size.